1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems that incorporate pipelines using dynamic logic.
2. Description of the Prior Art
Self-timed pipeline circuits employing a two-phase bundled data protocol were proposed by I. E. Sutherland in "Micropipelines", Communications of the ACM, Vol. 32, Number 6 June 1989, pp 720-738. The AMULET1 processor developed at the University of Manchester between 1991 and 1994 used a similar micropipeline design style. The AMULET1 processor is described in: S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, "A Micropipelined ARM", Proceedings of the IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration (VLSI '93), Grenoble, France, September 1993. Ed. Yanagawa, T. and Ivey, P. A. Pub. North Holland; S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, "AMULET1: A Micropipelined ARM", Proceedings of the IEEE Computer Conference, March 1994; and N. C. Paver, "The Design and Implementation of an Asynchronous Microprocessor", PhD Thesis, University of Manchester, June 1994. The AMULET1 processor also used two-phase control.
The AMULET1 processor employs dynamic logic techniques in some parts of its datapaths. However, since the delay-insensitive control circuit within such processors can stall in any state, extra circuitry is included (such as additional latches or charge retention circuitry) to give the dynamic circuits pseudo-static behavior. Dynamic circuits are considered desirable because they allow a particularly small and power efficient processor to be produced. However, these advantages are to some extent negated if additional circuitry needs to be provided to yield pseudo-static behavior.
Dynamic logic may be used without such additional circuitry providing certain conditions are met. Inherent charge leakage within dynamic logic circuits causes the output of the circuit to be valid for a short period of time. Accordingly, it has been proposed that the dynamic logic circuit should not begin evaluation until its output latch is free. Furthermore, the dynamic logic circuit also requires its inputs to be held stable until its evaluation is complete. The result of this is that a dynamic logic circuit constrains both its input latches and output latches when it is performing an evaluation.
FIG. 1 of the accompanying drawings illustrates a pipeline stage 2 incorporating a dynamic logic circuit 4. A latch circuit 6 latches the output data signals from the dynamic logic circuit 4 such that they are not lost through inherent charge leakage and then passes these output data signals onto the next pipeline stage. A pipeline stage control circuit 8 coordinates the operation of the dynamic logic circuit 4 and the latch circuit 6 with the neighboring pipeline stages.
FIGS. 2 and 3 of the accompanying drawings illustrate a pipeline composed of a number of the pipeline stages of FIG. 1 in operation. Considering FIG. 2, the dynamic logic circuits marked with a tick are active and in the process of evaluating output data signals from input data signals. The latch circuits marked with a tick are latching valid signals that are being evaluated by the following dynamic logic circuit. The latch circuits marked with a cross are waiting to receive the output data signals from their associated dynamic logic circuit.
Considering the pipeline stage 10, its active state is placing a constraint upon the latch circuits 12 and 14. Latch circuit 12 must maintain the inputs to the pipeline stage 10 and so latch circuit 12 is unavailable for its own dynamic logic circuit 16 which must therefore remain idle. The latch circuit 14 must be ready to receive the output data signals from the pipeline stage 10 and so is unavailable for maintaining the input data signals to the dynamic logic circuit 18. Accordingly, the dynamic logic circuit 18 must also remain idle.
FIG. 3 illustrates the situation that occurs when the pipeline stage 10 has completed its evaluation. The constraints upon the latch circuits 12 and 14 are now removed and providing the other conditions are met, then these two neighboring pipeline stages can then operate to evaluate signal values using their respective dynamic logic circuits 16 and 18. The analysis of the pipeline stage 10 can be extended by induction to all the pipeline stages. In this way, it will be seen that such systems are operating with, at best, half of the dynamic logic circuits being active at any one time.